Presently, electronic equipment is essential for many modern applications. Therefore, consumers are increasingly demanding more processing power, lower electrical power usage and cheaper devices. As the electronic industry strives to meet these demands and more complicated and denser configurations, miniaturization will result in an extension of the number of chips per wafer and the number of transistors per chip, as well as a reduction in power usage. Wafer level packaging (WLP) technology has been gaining popularity since the electronic components are being designed to be lighter, smaller, more multifunctional, more powerful, more reliable and less expensive. The WLP technology combines dies having different functionalities at a wafer level, and is widely applied in order to meet continuous demands toward the miniaturization and higher functions of the electronic components.
A substrate in WLP technology raises concerns about how to increase the number of the electric components, especially at the peripheral region of such substrate. In contrast to a traditional packaging technology, the electric components on the substrate with WLP technology are too crowded to locate any more components in peripheral region of the substrate. Thus, improvements in the method for a WLP continue to be sought.